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Micrel, Inc.
Pin Description: Signal Descriptions by Group
KSZ9692PB, KSZ9692PB-S
Pin Number
Pin Name
Pin Type
Pin Description
System Interface
R5
RESETN
I
Reset, asserted Low.
RESETN will force the KSZ9692PB, KSZ9692PB-S to reset ARM9 CPU and all
functional blocks. Once asserted, RESETN must remain asserted for a
minimum duration of 256 system clock cycles. When in the reset state, all the
output pins are put into Tri-state and all open drain signals are floated.
N5
WRSTO
O
Watchdog Timer Reset Output
When the Watchdog Timer expires, this signal will be asserted for at least 200
msec.
W1
XCLK2
I
System Clock Input 2.
External crystal or clock input 2. The clock frequency should be
25MHz ± 50ppm.
Y1
XCLK1
I
System Clock Input 1.
Used with XCLK1 pin when other polarity of crystal is needed. This is unused
for a normal clock input.
H19
Y15, Y14
CLK25MHz
DDCLKO[1:0]
O
O
25MHz output to external PHY
DDR Clock Out [1:0].
Output of the internal system clock, it is also used as the clock signal for DDR
interface.
W15, W14
DDCLKON[1:0]
O
The negative of differential pair of DDR Clock Out [1:0].
Output of the internal system clock, it is also used as the clock signal for DDR
interface.
U13
T7, U7
SDCLKEO
VREF
O
I
Clock Enable output for SDRAM (for Power Down Mode)
Reference Voltage for SSTL interface.
Must be half of the voltage for the DDR VDD supply. See EIA/JEDEC standard
EIA/JESD8-9 (Stub series terminated logic for 2.5V, SSTL_2)
W3
Y3
SDOCLK
SDICLK
O
I
DDR Clock Out for loopback from De-skew PLL
DDR Clock In from loopback to De-skew PLL. This pin must connect to
SDOCLK with appropriate de-skew length. See Engineering Evaluation Design
Kit for detailed implementation.
Y17, Y16
W17, W16
DDCLKO[3:2]
DDCLKON[3:2]
O
O
Factory Reserved.
Factory Reserved.
NAND/SRAM/ROM/EXIO Interface
L2, K1, K2,
J3, H5, H4,
J2, H3, J1,
H2, G5, H1,
G3, G4, G2,
SADDR[23..0]
O
SRAM Address Bus.
The 24-bit address bus covers 16M word memory space of
ROM/SRAM/FLASH, and 16M byte external I/O banks.
This address bus is shared between ROM/SRAM/FLASH/EXTIO devices.
F1, G1, F2,
F3, F5, F4,
E1, E2, E3
May 2011
10
M9999-051111-4.0
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